The Neotoma 1 MCU for FPGA

Release Versions and Notes

The Neotoma 1 processor is an Open Source small footprint load-store architecutre MCU using a stack in place of traditional registers for ALU operations. The MCU executes microcode instructions which are expanded from a more more traditional set of assembly language opcoces using the assembler.

The MCU address and data width, stack size, program RAM size, and data RAM size are all RTL parameters allowing for the MCU to be built sized appropriately for its intended use. The minimum address and data size is 8-bits to encode the instruction set.

The data stack is used for all ALU and I/O operations using its own RAM independent of the program and data RAM. The call stack resides in the data RAM and stack frames include optional local fucntion variables.

GPIO is accessed with a memory-mapped RAM load/store interface (system dependent). UART is accessed with a memory-mapped RAM load/store interface (system dependent).

The MCU is Harvard architecture where the program RAM, Scratch RAM (data RAM), and Stack RAM are all local to the MCU.

The MCU has a single and double word product multiply and has double word arithmetic shift instructions to help support fixed point arithmetic.

The assembler generates .hex files which can populate the the initial program and scratch memory RAM during synthesis.

The RAM arbiter also allows the program and scratch memroy to be programed at run time via the memory slave ports when the CPU is in reset.

RTL verification is directed test bench (DTB) self-checking simulation. The assembler verification is set of suite self-checking tests.

Synthesizable demo for the Digilent Basys3 Artix 7 FPGA prototyping board. The demo is a 16-bit counter displaying as four hex nibbles on the Basys3 seven sgement display. A button press will run a bubble sort on the four hex nibbles reordering them from hight to low. The demo include synthesis build scripts and debugging simulation scripts.

Xilinx Vivado is used for simulation, testbench, and synthesis.

The Neotoma 1 processor is released under the LGPL.